![]() When the comparison is in steady-state, and the output frequency and phase are matched to the incoming frequency and phase of the error detector, we say that the PLL is locked. In Figure 2 there is a negative feedback control loop operating in the frequency domain. In its most basic configuration, a phase-locked loop compares the phase of a reference signal (F REF) to the phase of an adjustable feedback signal (RF IN) F 0, as seen in Figure 1. Basic Configuration: Clock Clean-Up Circuit ![]() The article references the Analog Devices ADF4xxx and HMCxxx family of PLLs and voltage controlled oscillators (VCOs), and uses ADIsimPLL (Analog Devices in-house PLL circuit simulator) to demonstrate these different circuit performance parameters. This article explains some of the building blocks of phase locked loop circuits with references to each of these applications, in turn, to help guide the novice and phase locked loop expert alike in navigating part selection and the trade-offs inherent for each different application. Phase-locked loop (PLL) circuits exist in a wide variety of high frequency applications, from simple clock clean-up circuits, to local oscillators (LOs) for high performance radio communication links, and ultrafast switching frequency synthesizers in vector network analyzers (VNA). ![]()
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